On April 10, 2026, ASE Holding held a low-key groundbreaking ceremony for a new plant at the Renwu Industrial Park in Kaohsiung. Yet the significance of this event far exceeds most expectations: it represents not only ASE’s largest single capital investment in history, but also one piece of a vast global strategic map. In 2026, ASE will break ground on six new factories worldwide, setting a new corporate record for facility expansion. Meanwhile, Samsung announced a $4 billion investment in a packaging and testing plant in Vietnam; Amkor is accelerating the expansion of the world’s largest advanced packaging base; Micron’s India plant has officially entered production; and Intel’s advanced packaging complex in Malaysia is poised for launch.
In the past, packaging and testing (OSAT) was often regarded as the “back-end” of the semiconductor industry with relatively low technological content. Today, however, as the computing power race for AI IC approaches physical limits, advanced packaging has become the decisive factor in boosting performance, reducing power consumption, and breaking through the bottlenecks of Moore’s Law. A global battle for packaging and testing capacity is now in full swing.
This wave of OSAT capacity expansion is not an isolated move by individual companies, but a collective push across the entire industrial chain.
ASE is the most prominent frontrunner in this expansion. In 2026, the company plans to break ground on six new factories simultaneously, an all-time high. These facilities are strategically located across key global hubs, including the U.S., Malaysia, Japan, and Germany. The Kaohsiung Renwu plant alone involves a total investment of over NT$108.3 billion, with Phase I scheduled for launch in April 2027 and Phase II in October 2027. It is expected to generate an annual output value of NT$177.3 billion, mainly serving AI, high-performance computing, 5G communications, and automotive electronics. ASE’s Chief Operating Officer Tien-Yu Wu revealed that the company’s original 2026 capital expenditure of $7 billion “now has room for upward revision.”
Samsung is moving quickly to keep pace. According to Bloomberg on April 9, Samsung Electronics plans to invest $4 billion in a semiconductor packaging and testing plant in Thai Nguyen province, northern Vietnam, with an initial investment of $2 billion. This will mark Samsung’s largest single investment in the sector since entering Vietnam in 2008. Vietnam’s Ministry of Finance has confirmed it is in discussions with Samsung over semiconductor cooperation. The new plant will be located near Samsung’s existing smartphone production base, leveraging the region’s mature supply chain and infrastructure to meet growing global demand for packaged and tested IC in data centers and AI devices.
Micron has already delivered results. In late February, the company announced the official launch of its first semiconductor packaging and testing plant in Gujarat, India, with a total investment of $2.75 billion. Its Phase I cleanroom spans over 500,000 square feet, making it one of the world’s largest single-story OSAT facilities. Production capacity will reach tens of millions of units in 2026 and hundreds of millions in 2027. The first India-made memory modules have been delivered to Dell for use in locally produced laptops.
Intel is also accelerating its deployment. Its advanced packaging plant in Malaysia is 99% complete and expected to officially launch in the second half of 2026. With a total investment of approximately $7 billion, with an additional $200 million recently injected, the facility will fully support Intel’s core EMIB and Foveros packaging technologies. Plans include upgrading package size from 100×100 mm to 120×120 mm, increasing HBM stacks from 8 to 12, with long-term goals to support ultra-large packages accommodating 24 HBM stacks.
Data from Sigmaintell shows the global advanced packaging market is expected to reach $61.8 billion in 2026, a year-on-year increase of roughly 76%, with pricing momentum expected to continue at least through the end of 2026. Driven by demand from AI and high-performance computing, lead times for advanced packaging orders commonly exceed one year. As the industry continues to absorb backlogs, capacity expansion has become a top priority for all players. ASE even forecasts its advanced packaging and testing revenue will more than double from $1.6 billion in 2025 to over $3.2 billion in 2026.
Viewpoint: This is not cyclical capacity replenishment, but structural strategic positioning. As advanced processes approach physical limits, packaging has become the core path to improving IC integration, lowering power consumption, and enabling heterogeneous integration. Whoever controls advanced packaging capacity and technology holds the key to AI IC.
Capacity expansion is only one side of the coin; the other is the exponential rise in technical difficulty. The engineering realization of advanced packaging is far more complex than building a factory.
First are the yield and thermal challenges of HBM stacking. HBM4 will double its I/O count to 2,048, significantly increasing signal interference risks. According to Korean media, SK Hynix’s HBM4 encountered performance bottlenecks in 2.5D packaging testing, forcing delays in mass production. At the same time, 16-high HBM stacks generate extreme local heat density during operation, presenting unprecedented thermal design challenges. Samsung CTO Jae-Hyuk Song stated that hybrid bonding for 12-high and 16-high HBM can reduce base IC temperature by over 11%. However, the maturity and mass production capability of hybrid bonding remain industry-wide pain points.
Second is balancing package size and signal integrity. TSMC plans to launch a 5.5x reticle size CoWoS variant in 2026, with volume production of 9.5x reticle size solutions targeted for 2027. Larger package dimensions mean longer interconnect distances, higher signal attenuation risks, and more complex power delivery networks. Maintaining signal integrity in large-format packages is an engineering challenge facing all OSAT providers.
Third is the sharp rise in testing complexity. Advanced packaging integrates multiple IClets, HBM stacks, and high-density interconnects, making Final Test (FT) and System-Level Test (SLT) far more difficult than traditional single-IC packaging. Test equipment must verify not only individual IC functions but also the stability of multi-IC collaboration, power management efficiency, and thermal uniformity. This is the fundamental reason why ASE’s new Kaohsiung plant focuses on high-end semiconductor test services.
Viewpoint: Capacity can be built with capital, but yield and reliability require technical expertise and experience. The real barrier to advanced packaging is not whether IC can be packaged, but whether they can be packaged stably, accurately, and efficiently. This places comprehensive demands on back-end processes including testing, programming, and inspection.
As OSAT providers rush to build facilities, purchase equipment, and expand teams, a commonly overlooked fact is: the success of capacity expansion ultimately depends on the efficiency and quality of back-end processes.
Testing is the first line of defense for yield. A single advanced-packaged AI IC may integrate billions of transistors, multiple IClets, and multilayer HBM stacks. Even a minor defect in any section can result in total scrappage. Test equipment requires ultra-high-precision measurement, high-speed signal processing, and full fault coverage. Especially for HBM stack testing, each DRAM layer must be independently verified before packaging to ensure overall performance after integration.
Programming serves as the final quality gate before shipment. New-generation AI IC are commonly equipped with high-speed interfaces such as UFS 4.1 and LPDDR6, with data rates reaching multiple gigabytes per second. The programming process itself acts as a rigorous stress test for interface stability and memory reliability. A single programming failure can scrap an entire IC; data errors in a batch may lead to mass recalls. For automotive-grade IC, programming also requires full-process traceability to meet IATF 16949 standards.
Inspection acts as the infrared eye for visual quality. Packaged IC may exhibit defects such as poor coplanarity, adhesive overflow, or surface scratches. High-precision optical inspection systems can catch these defects before shipment, preventing quality issues from reaching customers.
This is the field where HiloMax Semiconductor has long focused. With four decades of technological heritage, HiloMax is a provider of IC programming equipment, test systems, and automation solutions, covering the full lifecycle from IC design verification and R&D to mass production and after-sales support. In 2025, we pioneered the launch of a proprietary programming core supporting UFS 4.1, securing a position for domestic equipment in high-end memory IC programming. Leveraging contract programming service centers in Xuzhou, Suzhou, Shenzhen, and Vietnam, HiloMax provides a solid technical foundation and efficient delivery support for OSAT capacity expansion through a model of independent R&D, localized manufacturing, and complete contract manufacturing support.
Viewpoint: The capacity race among OSAT providers is ultimately not just about factory space and equipment quantity, but about the efficiency and quality of back-end processes. In this sense, test and programming equipment suppliers are not bystanders, but key participants in this competition.
ASE COO Tien-Yu Wu described 2026 as an “extremely busy year” for the group — a statement that applies equally to the entire OSAT industry. From Kaohsiung to Vietnam, India to Malaysia, the pace of expansion among industry giants is accelerating.
For industry practitioners, however, a more critical question emerges: once capacity is in place, who will guarantee the yield and reliability of each IC? Who can provide full-process support from testing to programming? This may be the most profound issue worth watching in this “OSAT battle.”
What is your view on the current trend of OSAT capacity expansion? Which technical challenge in advanced packaging do you think is most likely to become a bottleneck in volume ramp-up? Feel free to share your observations and practical experience in the comments section.
