Newly recruited test engineers sometimes scratch their heads over test data: why do IC that perform perfectly in CP testing start to fail in FT? Or the other way around—CP yield is just average, yet FT passes without a hitch. More often than not, this is not because the test program is wrong, but because they haven’t truly understood the different roles CP and FT play in the overall IC manufacturing flow. Simply put, they are two critical inspections during a IC’s “birth” and “maturity” stages, with completely different purposes, methods, and standards.
Today we’ll clarify the core differences between the two.
Stage and Target: From Collective Preliminary Screening to Individual Final Inspection
The most fundamental difference lies in the timing and object of testing.
CP testing, short for IC Probing, also known as wafer sort. It takes place before IC packaging. Engineers use a precision probe card to directly contact the pads of each die on the wafer, testing bare dies that are still in a “connected” state on the wafer. You can think of it as the first collective screening for IC before they move to assembly.
FT testing, short for Final Test. It occurs after the IC are fully packaged into independent units. The IC is placed into a test socket, and testing is performed through its external pins. This is the final comprehensive qualification for IC before being delivered to customers.
Purpose and Strategy: Protecting Core Yield vs. Ensuring Final Quality
Because of the different stages, the two have strategically distinct core goals.
The primary goal of CP testing is to save cost. Wafer manufacturing is expensive. Packaging defective dies would simply waste assembly cost. The core task of CP is to mark dies with obvious functional failures or severe defects before packaging (usually with ink dots or electronic maps) so they can be rejected in later processes. CP focuses on the most essential circuit functions and key parameters, serving as a fast screening for critical issues.
The ultimate goal of FT testing is to guarantee quality. By this stage, packaging cost has already been invested, and the IC must face customers in its final form. FT ensures every delivered IC fully meets all requirements in the datasheet for performance, reliability, and AC/DC characteristics. Testing is more comprehensive and stricter, verified under real-world conditions through packaged pins.
Technical Implementation: Probes vs. Pins
Different objectives are directly reflected in test hardware and environment.
1. Test Interface: CP uses a probe card with ultra-fine tips that directly contact micron-scale aluminum or copper pads. FT uses a test socket that connects to formed, relatively thick package pins. This means CP is more sensitive to contact resistance and parasitic parameters, posing greater challenges to signal integrity.
2. Test Environment: Since CP tests bare dies, they are usually performed at room temperature, with limited high/low-temperature testing (except for engineering verification). FT, however, must cover the full temperature range specified in the product datasheet (such as -40℃, 25℃, 85℃) to verify stability across operating temperatures.
3. Test Speed and Parallelism: To improve efficiency, CP uses high parallelism, testing dozens or even hundreds of dies at once. Although FT also supports parallel testing, the number is usually lower due to test socket cost and thermal constraints, but individual test items tend to be more thorough.
In summary, CP is economical screening, focusing on quick rejection to protect front-end results and avoid subsequent waste. FT is quality release, emphasizing full verification to safeguard brand reputation and customer satisfaction. Only by combining data from both can we fully plot the IC manufacturing yield curve and provide precise feedback for front-end process improvement and back-end quality enhancement.
A question for you: Have you ever encountered inverted CP and FT yields in your projects? For example, high CP yield but low FT yield—what could be the cause? Is it stress damage introduced during packaging, or do fundamental differences in test conditions (temperature, signal loading) expose insufficient design margin? Feel free to share your practical experience and analysis in the comments; let’s discuss together.
